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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
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hd404818 series 4-bit single-chip microcomputer preliminary rev. 2.0 sept. 1998 description t he h d4 04 81 8 se ri es of 4-bit single-chip hmcs400 series microcomputers provide high program productivity. it incorporates a large size memory, lcd controller/driver, voltage comparator, and 32-khz watch oscillator circuit. the hd404818 series has both standard voltage versions and low voltage versions available. the standard voltage versions operate at 4.0 v to 6.0 v (mask rom version) and 4.0 v to 5.5 v (prom version), while the low voltage versions operate at 2.7 v to 6.0 v (mask rom) and 3.0 v to 5.5 v (prom). low voltage versions include an l in their product name. standard voltage versions: hd404812, hd404814, hd404816, hd404818, hd4074818 low voltage versions: hd40l4812, hd40l4814, hd40l4816, hd40l4818, hd407l4818 the hd4074818 and hd407l4818, containing proms, are ztat ? microcomputers which can dramatically shorten system development time and smoothly proceed from debugging to mass production. ztat tm : zero turn around time ztat is a trademark of hitachi ltd. features 2048-word 10-bit rom (hd404812, hd40l4812) 4096-word 10-bit rom (hd404814, hd40l4814) 6144-word 10-bit rom (hd404816, hd40l4816) 8192-word 10-bit rom (hd404818, hd40l4818, hd4074818, hd407l4818) 1184-digit 4-bit ram 30 i/o pins, including 10 high-current output pins, all cmos and programmable as i/o pull-up mos lcd controller/driver (32 segments 4 commons) three timer/counters clock-synchronous 8-bit serial interface six interrupt sources ? two by external sources ? four by internal sources
hd404818 series 2 subroutine stack up to 16 levels, including interrupts instruction cycle time: ? 1 m s (f osc = 4 mhz for hd404812/hd404814/hd404816/hd404818/hd4074818) ? 5 m s (f osc = 800 khz for hd40l4812/hd40l4814/hd40l4816/hd40l4818/hd407l4818) four low-power dissipation modes ? standby mode ? stop mode ? watch mode ? subactive mode internal oscillator: ? main clock: can be driven by ceramic oscillator, crystal oscillator, or external clock ? subclock: 32.768-khz crystal voltage comparator (2 channels) package ? 80-pin plastic flat package (fp-80b, fp-80a) ? 80-pin plastic thin flat package (tfp-80)
hd404818 series 3 ordering information type supply voltage product name model name rom (word) clock frequency package mask rom standard (4.0 to 6.0 v) hd404812 hd404812fs 2,048 4 fp-80b hd404812h fp-80a hd404812tf tfp-80 hd404814 hd404814fs 4,096 fp-80b hd404814h fp-80a hd404814tf tfp-80 hd404816 hd404816fs 6,144 fp-80b hd404816h fp-80a hd404816tf tfp-80 hd404818 hd404818fs 8,192 fp-80b HD404818H fp-80a hd404818tf tfp-80 low-voltage operation hd40l4812 hd40l4812fs 2,048 0.8 fp-80b (2.7 to 6.0 v) hd40l4812h fp-80a hd40l4812tf tfp-80 hd40l4814 hd40l4814fs 4,096 fp-80b hd40l4814h fp-80a hd40l4814tf tfp-80 hd40l4816 hd40l4816fs 6,144 fp-80b hd40l4816h fp-80a hd40l4816tf tfp-80 hd40l4818 hd40l4818fs 8,192 fp-80b hd40l4818h fp-80a hd40l4818tf tfp-80 ztat ? standard (4.0 to 5.5 v) hd4074818 hd4074818fs 8,192 4 fp-80b hd4074818h fp-80a hd4074818tf tfp-80 low-voltage operation hd407l4818 hd407l4818fs 0.8 fp-80b (3.0 to 5.5 v) hd407l4818h fp-80a hd407l4818tf tfp-80
hd404818 series 4 pin arrangement d reset osc osc v v v com4 v numg numo numo com3 com2 com1 d 1 0 2 cc 3 2 1 r2 r2 r2 r3 seg2 seg3 seg4 seg5 timo/r3 int /r3 int /r3 seg1 seg6 seg7 seg8 r2 3 0 2 1 2 1 0 0 3 1 1 1 2 3 4 5 6 7 8 9 10 11 12 14 13 15 17 16 18 20 19 22 21 24 23 64 63 62 61 60 59 58 57 56 55 54 53 51 52 50 48 49 47 45 46 43 44 41 42 26 27 28 29 34 35 36 37 30 31 32 33 38 39 40 25 79 78 77 76 71 70 69 68 75 74 73 72 67 66 65 80 (top view) seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 d d d vc /d comp0/d comp1/d x1 test x2 sck /r0 gnd si/r0 r0 so/r0 r1 r1 r1 r1 2 4 5 6 7 8 9 10 11 12 13 0 1 2 3 0 1 2 3 ref d d d d 3 d d 1 2 3 4 5 6 7 8 9 10 11 12 14 13 15 17 16 18 20 19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47 48 46 44 45 43 41 42 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (top view) d d d reset v v v osc v com4 com3 d 3 2 3 2 1 2 numg com2 com1 seg32 seg31 1 0 osc 1 cc numo numo r2 r2 r2 r3 seg2 seg3 seg4 seg5 timo/r3 int /r3 int /r3 seg1 seg6 seg7 seg8 r2 3 0 2 1 2 1 0 0 1 seg9 seg10 r1 r1 3 3 2 d d d d d 4 5 6 7 8 9 d 10 d 11 vc /d ref comp0/d comp1/d 12 13 test x1 x2 gnd sck /r0 0 si/r0 1 so/r0 2 r0 3 r1 0 r1 1 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 fp-80b tfp-80 fp-80a
hd404818 series 5 pin description pin number pin number fp-80b fp-80a, tfp-80 pin name i/o fp-80b fp-80a, tfp-80 pin name i/o 179 d 2 i/o 31 29 r3 2 / int 0 i/o 280 d 3 i/o 32 30 r3 3 / int 1 i/o 31 d 4 i/o 33 31 seg1 o 42 d 5 i/o 34 32 seg2 o 53 d 6 i/o 35 33 seg3 o 64 d 7 i/o 36 34 seg4 o 75 d 8 i/o 37 35 seg5 o 86 d 9 i/o 38 36 seg6 o 97 d 10 i 3 9 3 7 seg7 o 10 8 d 11 /vc ref i 4 0 3 8 seg8 o 11 9 d 12 /comp 0 i 4 1 3 9 seg9 o 12 10 d 13 /comp 1 i 4 2 4 0 seg10 o 13 11 test i 4 3 4 1 seg11 o 14 12 x1 i 4 4 4 2 seg12 o 15 13 x2 o 4 5 4 3 seg13 o 16 14 gnd 46 44 seg14 o 17 15 r0 0 / sck i/o 47 45 seg15 o 18 16 r0 1 /si i/o 48 46 seg16 o 19 17 r0 2 /so i/o 49 47 seg17 o 20 18 r0 3 i/o 50 48 seg18 o 21 19 r1 0 i/o 51 49 seg19 o 22 20 r1 1 i/o 52 50 seg20 o 23 21 r1 2 i/o 53 51 seg21 o 24 22 r1 3 i/o 54 52 seg22 o 25 23 r2 0 i/o 55 53 seg23 o 26 24 r2 1 i/o 56 54 seg24 o 27 25 r2 2 i/o 57 55 seg25 o 28 26 r2 3 i/o 58 56 seg26 o 29 27 r3 0 i/o 59 57 seg27 o 30 28 r3 1 /timo i/o 60 58 seg28 o
hd404818 series 6 pin number pin number fp-80b fp-80a, tfp-80 pin name i/o fp-80b fp-80a, tfp-80 pin name i/o 61 59 seg29 o 7 1 6 9 v 3 62 60 seg30 o 7 2 7 0 numo 63 61 seg31 o 7 3 7 1 numo 64 62 seg32 o 7 4 7 2 numg 65 63 com1 o 7 5 7 3 v cc 66 64 com2 o 7 6 7 4 osc 1 i 67 65 com3 o 7 7 7 5 osc 2 o 68 66 com4 o 7 8 7 6 reset i 69 67 v 1 79 77 d 0 i/o 70 68 v 2 80 78 d 1 i/o note: i/o: input/output pin, i: input pin, o: output pin, numo: open, numg: gnd
hd404818 series 7 pin functions power supply v cc : apply the v cc power supply voltage to this pin. gnd: connect to ground. test : for test purposes only. connect it to v cc . reset: mcu reset pin. refer to the reset section for details. numg: non-user pin. connect it to gnd. numo: non-user pin. do not connect it to any lines. oscillators osc 1 , osc 2 : internal oscillator input pins. they both can be connected to a crystal, ceramic resonator, or external oscillator circuit. refer to the internal oscillator circuit section for details. x1, x2: watch oscillator 32-khz crystal pins. ports d 0 ? 13 (d port): fourteen 1-bit i/o ports. d 0 to d 9 are i/o ports and d 10 to d 13 are input ports. d 0 ? 9 are high current output ports (15 ma max.). d 11 ? 13 are also available as voltage comparators. refer to the input/output section for details. r0?3 (r ports): 4-bit i/o ports. r0 0 , r0 1 , r0 2 , r3 1 , r3 2 , and r3 3 are multiplexed with sck , si, so, timo, int 0 , and int 1 , respectively. interrupts int 0 , int 1 : external interrupt pins. int 1 can be used as an external event input pin for timer b. int 0 and int 1 are multiplexed with r3 2 and r3 3 , respectively. for details, see the interrupts section. serial interface sck , si, so: the transmit clock i/o pin ( sck ), serial data input pin (si), and serial data output pin (so) are used for serial interface. sck , si, and so are multiplexed with r0 0 , r0 1 , and r0 2 , respectively. for details, see the serial interface section. timer timo: variable duty-cycle pulse waveform output pin. see the timer c section for details.
hd404818 series 8 lcd driver/controller v 1 , v 2 , v 3 : power supply pins for the lcd driver. since the lcd driving resistors are provided internally, no lines should be connected to these pins. the voltage on each pin is v cc 3 v 1 3 v 2 3 v 3 3 gnd. see the liquid crystal display section for details. com1 to com4: common signal output pins for the lcd display. see the liquid crystal display section for details. seg1 to seg32: segment signals output pins for the lcd display. see the liquid crystal display section for details. voltage comparator comp 0 , comp 1 , vc ref : analog input pins for the voltage comparator. vc ref is used as a reference voltage pin to input the threshold voltage of the analog input pin.
hd404818 series 9 block diagram internal address bus system control circuit ram (1,184 4 bits) w (2 bits) x (4 bits) spx (4 bits) y (4 bits) spy (4 bits) ca (1 bit) st (1 bit) a (4 bits) b (4 bits) sp (10 bits) instruction decoder pc (14 bits) rom (2,048 10 bits) (4,096 10 bits) (6,144 10 bits) (8,192 10 bits) d port alu cpu int 0 int 1 timer b timer c timo d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 r0 port r0 0 r0 1 r0 2 r0 3 r1 port r1 0 r1 1 r1 2 r1 3 r2 port r2 0 r2 1 r2 2 r2 3 r3 port r3 0 r3 1 r3 2 r3 3 reset test osc osc x1 x2 v cc gnd timer a external interrupt control circuit internal data bus internal data bus high- current pins lcd driver circuit v 1 v 2 v 3 com1 com2 com3 com4 seg1 seg2 seg3 seg31 seg32 vc ref compa- rator serial interface si so sck : data bus : signal lines 1 2 comp 0 comp 1 d 12 d 13
hd404818 series 10 memory map rom memory map the rom is described in the following paragraphs with the rom memory map in figure 1. 0 15 16 63 64 4095 4096 8191 8192 16383 0 $000f $0fff $1000 $1fff $2000 $3fff $0010 $003f $0040 vector address zero-page subroutine (64 words) pattern (4096 words) program not used 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset routine) jmpl instruction (jump to int routine) 0 jmpl instruction (jump to timer a routine) 1 jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to serial routine) jmpl instruction (jump to int routine) * hd404812, hd40l4812: 2048 words hd404814, hd40l4814: 4096 words hd404816, hd40l4816: 6144 words hd404818, hd40l4818, hd4074818, hd407l4818: 8192 words * note: figure 1 rom memory map vector address area ($0000 to $000f): locations $0000 through $000f are reserved for jmpl instructions to branch to the starting address of the initialization program and of the interrupt programs. after reset or an interrupt routine, the program is executed from the vector address. zero-page subroutine area ($0000 to $003f): locations $0000 through $003f are reserved for subroutines. the program sequence branches to subroutines by the cal instruction. pattern area ($0000 to $0fff): locations $0000 through $0fff are reserved for rom data. the p instruction allows the mcu to reference rom data as a pattern. program area ($0000 to $07ff: hd404812, hd40l4812; $0000 to $0fff: hd404814, hd40l4814; $0000 to $17ff: hd404816, hd40l4816; $0000 to $1fff: hd404818, hd40l4818, hd4074818, hd407l4818): used for program coding.
hd404818 series 11 ram memory map the mcu also contains a 1,184-digit 4-bit ram as the data and stack area. in addition to these areas, interrupt control bits and special function registers are mapped on the ram memory space. the ram memory map (figure 2) is described in the following paragraphs. interrupt control bits area ($000 to $003): the interrupt control bits area (figure 3) is used for interrupt control. it is accessible only by ram bit manipulation instructions. however, the interrupt request flag cannot be set by software. the rsp bit is used only to reset the stack pointer. special function registers area ($004 to $01f, $024 to $03f): the special function registers are the mode or data registers for the serial interface, timer/counters, lcd, and the data control registers for the i/o ports. these registers are classified into three types: write-only, read-only, and read/write as shown in figure 2. the sem/rem and semd/remd instructions are available for the lcd control register (lcr). other registers cannot be accessed by ram bit manipulation instructions. register flag area ($020 to $023): consist of the lson, wdon, tgsp, and dton flags which are bit registers accessible by the ram bit manip ula tion instruction. the wdon flag can only be set, and only by the sem/semd instruction. the dton flag can be set, reset, and tested by the sem/semd, rem/remd, and tmd instructions. note that the dton flag is active only in subactive mode, and is normally reset in active mode. lcd data area ($050 to $06f): locations $050 to $06f store the lcd data which is automatically transmitted to the segment driver as display data. the lcd is illuminated with 1s and faded with 0s. this area can be used as a data area. data area ($040 to $2cf, $100 to $2cf; bank 0/1): the 16 digits of $040 through $04f are called memory registers (mr) and are accessible by the lamr and xmra instructions (figure 4). 464 digits of $100 through $2cf are selected as bank 0 or 1 depending on the value of the v register. stack area ($3c0 to $3ff): locations $3c0 through $3ff are reserved for lifo stacks to save the contents of the program counter (pc), status flag (st), and carry flag (ca) when subroutine calls (cal or call instruction) and interrupts are processed. this area can be used as a 16-level nesting stack in which one level requires 4 digits. figure 4 shows the save condition. the program counter is restored by the rtn and rtni instructions. the status and carry flags are restored only by the rtni instruction. this area, when not used as a stack, is available as a data area.
hd404818 series 12 0 $000 $000 63 64 80 112 959 960 1023 $03f $040 $050 $070 $3ff 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 16 17 32 35 48 18 19 20 49 50 51 63 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $020 $023 $030 $031 $032 $033 $03b $03c $03d $03f $00a $00b $00e $00f w w r/w w w w w w w w w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w r/w $100 $2cf 61 59 60 $3bf $3c0 $2cf ram-mapped registers memory registers (mr) lcd display area (32 digits) data (144 digits) data (464 digits 2) v = 0 (bank 0) v = 1 (bank 1) not used stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register (smr) serial data register lower (srl) serial data register upper (sru) timer mode register a (tma) timer mode register b (tmb) timer b (tcbl/tlrl) (tcbu/tlru) miscellaneous register (mis) timer mode register c (tmc) timer c (tccl/tcrl) (tccu/tcru) not used not used port mode register b (pmrb) lcd control register (lcr) lcd mode register (lmr) not used register flag area not used port r0 dcr (dcr0) port r1 dcr (dcr1) port r2 dcr (dcr2) port r3 dcr (dcr3) not used port d ? dcr (dcrb) port d ? dcr (dcrc) port d ? dcr (dcrd) not used v register (v-reg) 03 47 89 data (464 digits) v = 1 (bank 1) data (464 digits) v = 0 (bank 0) note: do not use any area labelled "not used". 10 11 14 15 timer counter b lower (tcbl) timer counter b upper (tcbu) timer counter c lower (tccl) timer counter c upper (tccu) timer load register b lower (tlrl) timer load register b upper (tlru) timer load register c lower (tcrl) timer load register c upper (tcru) r: w: r/w: $100 read only write only read/write the data area has two banks: bank 0 (v = 0) and bank 1 (v = 1) figure 2 ram memory map (1,184-digit 4-bit)
hd404818 series 13 0 1 2 3 bit 3 bit 2 bit 1 bit 0 im0 (im of int ) 0 if0 (if of int ) 0 rsp (reset sp bit) ie (interrupt enable flag) imta (im of timer a) ifta (if of timer a) im1 (im of int ) 1 if1 (if of int ) 1 imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) not used not used ims (im of serial) ifs (if of serial) $000 $001 $002 $003 32 dton direct transfer on flag not used wdon (watchdog on flag) lson (low speed on flag) not used $020 $021 $023 if: im: ie: sp: note: bits in the interrupt control bits area and register flag area are set by the sem or semd instruction, reset by the rem or remd instruction, and tested by the tm or tmd instruction. other instructions have no effect. however, note the following usage limitations of ram bit manipulation instructions. interrupt request flag interrupt mask interrupt enable flag stack pointer if rsp wdon dton sem/semd not executed not executed allowed not executed in active mode used in subactive mode rem/remd allowed allowed not executed allowed tm/tmd allowed inhibited inhibited allowed note: wdon is reset only by mcu reset. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 3 configuration of interrupt control bits and register flag areas
hd404818 series 14 pc to pc : st: ca: 13 0 memory registers stack area 64 $040 960 $3c0 65 $041 66 $042 67 $043 68 $044 69 $045 70 $046 71 $047 72 $048 73 $049 74 $04a 75 $04b 76 $04c 77 $04d 78 $04e 79 $04f mr (0) mr (1) mr (2) mr (3) mr (4) mr (5) mr (6) mr (7) mr (8) mr (9) mr (10) mr (11) mr (12) mr (13) mr (14) mr (15) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 1023 $3ff st pc 10 pc 13 pc 12 pc 11 ca pc 3 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 2 pc 1 pc 0 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff 1022 1023 1020 1021 program counter status flag carry flag figure 4 configuration of memory registers, stack area, and stack position
hd404818 series 15 functional description registers and flags the mcu provides ten registers and two flags for cpu operations. they are illustrated in figure 5 and described in the following paragraphs. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 (v) 0 0 initial value: undefined, r/w initial value: undefined, r/w v register initial value: 0, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 5 registers and flags accumulator (a), b register (b): the accumulator and b register are 4-bit registers which hold the results of the arithmetic logic unit (alu), and exchange data between memory, i/o, and other registers.
hd404818 series 16 v register (v): the v register, available for ram address expansion, selects the bank of locations $100 $2cf on the ram address (464 digits) depending on its value. therefore, when accessing locations $100 $2cf on the ram address, specify the value of the v register (v = $0: bank 0; v = $1: bank 1). locations $000?0ff and $300?3ff can be accessed independently of the v register. the v register is located at $03f of the ram address area. w register (w), x register (x), y register (y): the 2-bit w register and 4-bit x and y registers address ram indirectly. the y register is also available for addressing port d. spx register (spx), spy register (spy): the 4-bit spx and spy registers are available for assisting the x and y registers, respectively. carry flag (ca): the carry flag holds the alu overflow generated by an arithmetic operation. it is also affected by the sec, rec, rotl, and rotr instructions. during an interrupt, the carry flag is pushed onto the stack and restored back from the stack by the rtni instruction. (it is unaffected by the rtn instruction.) status flag (st): the status flag holds the alu overflow, alu non-zero, and the results of a bit test instruction for arithmetic or compare instructions. the status flag is a branch condition of the br, brl, cal, or call instruction. the value of the status flag remains unchanged until an instruction which affects the next status is executed. the status flag becomes 1 after the br, brl, cal, or call instruction is either executed or skipped. during an interrupt, the status flag is pushed onto the stack and restored back from the stack by the rtni instruction, not by the rtn instruction. program counter (pc): the program counter is a 14-bit binary counter for holding the rom address. stack pointer (sp): the stack pointer is a 10-bit register to indicate the next stacking area up to 16 levels. the stack pointer is initialized to ram address $3ff at mcu reset. it is decremented by 4 as data is pushed onto the stack, and incremented by 4 as data is restored back from the stack. the stack pointer is initialized to $3ff either by mcu reset or by the rsp bit reset from the rem/remd instruction.
hd404818 series 17 reset setting the reset pin high resets the mcu. at power-on or when cancelling the stop mode for the oscillator, apply the reset input for at least t rc for the oscillator to stabilize. in all other cases, at least two instruction cycles of reset input are required for the mcu reset. table 1 shows the components initialized by mcu reset, and each of its status. table 1 initial values after mcu reset items initial value contents program counter (pc) $0000 execute program from the top of the rom address status flag (st) 1 enable branching with conditional branch instructions stack pointer (sp) $3ff stack level is 0 v register (bank register) (v) 0 bank 0 (memory) interrupt flags/mask interrupt enable flag (ie) 0 inhibit all interrupts interrupt request flag (if) 0 no interrupt request interrupt mask (im) 1 masks interrupt request i/o port data register (pdr) all bits are 1 enable to transmit high data control register (dcr) all bits are 0 output buffer is off (high impedance) port mode register a (pmra) 0000 see port mode register a section port mode register b (pmrb) 0000 see port mode register b section timer/counters, serial interface timer mode register a (tma) 0000 see timer mode register a section timer mode register b (tmb) 0000 see timer mode register b section timer mode register c (tmc) 0000 see timer mode register c section serial mode register (smr) 0000 see serial mode register section prescaler s $000 prescaler w $00 timer counter a (tca) $00 timer counter b (tcb) $00 timer counter c (tcc) $00 timer load register b (tlr) $00 timer load register c (tcr) $00 octal counter 000
hd404818 series 18 table 1 initial values after mcu reset (cont) items initial value contents lcd lcd control register (lcr) 000 refer to description of lcd control register lcd mode register (lmr) 0000 refer to description of lcd duty/clock control bit register low speed on flag (lson) 0 refer to description of low-power dissipation mode watchdog timer on flag (wdon) 0 refer to description of timer c direct transfer on flag (dton) 0 refer to description of low-power dissipation mode miscellaneous register (mis) 000 item after mcu reset to recover from stop mode after mcu reset to recover from other modes carry flag (ca) the contents of the items before mcu reset are not retained. it is necessary to initialize them by software. the contents of the items before mcu reset are not retained. it is necessary to initialize them by software. accumulator (a) b register (b) w register (w) x/spx registers (x/spx) y/spy registers (y/spy) serial data register (sr) ram the contents of ram before mcu reset (just before stop instruction) are retained.
hd404818 series 19 interrupts six interrupt sources are available on the mcu: external requests ( int 0 , int 1 ), timer/counters (timers a, b, and c), and the serial interface. for each source, an interrupt request flag (if), interrupt mask (im), and interrupt vector addresses are provided to control and maintain the interrupt request. the interrupt enable flag (ie) is also used to control interrupt operations. interrupt control bits and interrupt servicing: the interrupt control bits are mapped on $000 through $003 by the ram space. they are accessible by ram bit manipulations instructions, although the interrupt request flag (if) cannot be set by software. the interrupt enable flag (ie) and if are cleared to 0, and the interrupt mask (im) is set to 1 after mcu reset. figure 6 is a block diagram of the interrupt control circuit. table 2 shows the interrupt priority and vector addresses, and table 3 shows the interrupt conditions corresponding to each interrupt source. the interrupt request is generated when if is set to 1 and im is 0. if ie is 1 at this time, the interrupt will be activated and vector addresses will be generated from the priority pla corresponding to the interrupt sources.
hd404818 series 20 ie if0 im0 if1 im1 ifta imta iftb imtb iftc imtc ifs ims $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 sequence control ?push pc/ca/st ?reset ie ?jump to vector address priority control logic vector address note: $m, n is ram address $m, bit number n. figure 6 interrupt control circuit block diagram table 2 vector addresses and interrupt priority reset/interrupt priority vector addresses reset $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b 4 $0008 timer c 5 $000a serial 6 $000c
hd404818 series 21 table 3 interrupt conditions interrupt source interrupt control bit int 0 int 1 timer a timer b timer c serial ie 111111 if0 im0 100000 if1 im1 * 10000 ifta imta ** 1000 iftb imtb *** 100 iftc imtc **** 10 ifs ims ***** 1 note: * don? care. figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. if an interrupt is requested, the instruction being executed finishes in the first cycle. the ie is reset in the second cycle. in the second and third cycles, the carry flag, status flag, and program counter are pushed onto the stack. in the third cycle, the instruction is executed after jumping to the vector address. in each vector address, program the jmpl instruction to branch to the starting address of the interrupt program. the if, which caused the interrupt, must be reset by software in the interrupt program. instruction cycles 123456 instruction execution stacking; reset of ie interrupt acceptance jmpl instruction execution on the vector address instruction execution at starting address of the interrupt routine stacking; vector address generated figure 7 interrupt processing sequence
hd404818 series 22 power on reset = 1 ? reset mcu interrupt request ? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $0008 ? pc $000a ? pc $000c ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int interrupt ? 0 int interrupt ? 1 timer a interrupt ? timer b interrupt ? timer c interrupt ? no yes no yes no yes yes yes yes yes yes no no no no no ? ? ? (serial interrupt) figure 8 interrupt processing flowchart
hd404818 series 23 interrupt enable flag (ie: $000, bit 0): the interrupt enable flag enables/disables interrupt requests (table 4). it is reset by an interrupt and set by the rtni instruction. table 4 interrupt enable flag ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 ): the external interrupt request inputs ( int 0 , int 1 ) can be selected by port mode register a (pmra: $004). the external interrupt request flags (if0, if1) are set at the falling edge of i nt 0 and i nt 1 inputs, respectively (table 5). the int 1 input can be used as a clock signal input to timer b, in which timer b counts up at each falling edge of the int 1 input. when using int 1 as the timer b external event input, the external interrupt mask (im1) has to be set so that the interrupt request by int 1 will not be accepted (table 6). more than two instruction cycle times (2t cyc /2t subcyc ) are needed to detect the edge of int 0 or int 1 . external interrupt request flags (if0: $000, bit 2; if1: $001, bit 0): the external interrupt request flags (if0, if1) are set at the falling edge of the int 0 and int 1 inputs, respectively (table 5). table 5 external interrupt request flags if0, if1 interrupt request 0no 1 yes external interrupt masks (im0: $000, bit 3; im1: $001, bit 1): the external interrupt masks mask the external interrupt requests (table 6). table 6 external interrupt masks im0, im1 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): the timer a interrupt request flag is set by the overflow output of timer a (table 7).
hd404818 series 24 table 7 timer a interrupt request flag ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): the timer a interrupt mask prevents an interrupt request from being generated by the timer a interrupt request flag (table 8). table 8 timer a interrupt mask imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): the timer b interrupt request flag is set by the overflow output of timer b (table 9). table 9 timer b interrupt request flag iftb interrupt request 0no 1 yes timer b interrupt mask (imtb: $002, bit 1): the timer b interrupt mask prevents an interrupt request from being generated by the timer b interrupt request flag (table 10). table 10 timer b interrupt mask imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): the timer c interrupt request flag is set by the overflow output of timer c (table 11). table 11 timer c interrupt request flag iftc interrupt request 0no 1 yes
hd404818 series 25 timer c interrupt mask (imtc: $002, bit 3): the timer c interrupt mask prevents the interrupt from being generated by the timer c interrupt request flag (table 12). table 12 timer c interrupt mask imtc interrupt request 0 enabled 1 disabled (masked) serial interrupt request flag (ifs: $003, bit 0): the serial interrupt request flag is set when the octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal counter (table 13). table 13 serial interrupt request flag ifs interrupt request 0no 1 yes serial interrupt mask (ims: $003, bit 1): the serial interrupt mask masks the interrupt request (table 14). table 14 serial interrupt mask ims interrupt request 0 enabled 1 disabled (masked)
hd404818 series 26 operating modes the mcu has five operating modes that are specified by how the clock is used. the functions available in each mode are listed in table 15, and operations are shown in table 16. transitions between operating modes are shown in figure 9. table 16 provides additional information for table 26. table 15 functions available in each operating mode mode name active standby stop watch subactive * 4 activation method reset cancellation, interrupt request sby instruction tma3 = 0, stop instruction tma3 = 1, stop instruction int 0 or timer a interrupt request from watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op op * 1 op op instruction execution ( cpu ) op stopped stopped stopped op peripheral function, interrupt ( per ) op op stopped stopped op clock function, interrupt ( clk ) op op stopped op * 2 op * 2 ram op retained retained retained op registers/flags op retained reset retained op i/o op retained high impedance * 3 retained * 3 op * 3 cancellation method reset input, stop/sby instruction reset input, interrupt request reset input reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: op indicates operating. 1. to reduce current dissipation, stop all oscillation in external circuits. 2. refer to the interrupt frame section for details. 3. refer to interrupt frame. 4. subactive mode is an optional function to be specified on the function option list. 5. in the watch and subactive modes, the mcu requires a 32.768-khz crystal oscillator.
hd404818 series 27 table 16 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode * 2 cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op serial interface reset stopped * 3 op op lcd reset op op op i/o reset * 1 retained retained op notes: op indicates operating. 1. output pins are at high impedance. 2. subactive mode is an optional function to be specified on the function option list. 3. transmission/reception is activated if a clock is input in external clock mode. (however, interrupts are stopped.) table 17 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode d 0 ? 9 retained high impedance input enabled d 10 ? 13 input enabled r0?3 retained high impedance input enabled system clock ( cpu ) operating stopped non-time-base peripheral function clock ( per ) operating active mode standby mode subactive mode stopped watch mode (tma3 = 1) stop mode (tma3 = 0)
hd404818 series 28 reset f : f : : : : cpu clk per osc x operating operating stopped f f cyc cyc f : f : : : : cpu clk per osc x operating operating stopped f f sub cyc f : f : : : : cpu clk per osc x operating operating f f f cyc cyc cyc f : f : : : : cpu clk per osc x operating operating f f f cyc sub cyc f : f : : : : cpu clk per osc x stopped operating f f f sub sub sub f : f : : : : cpu clk per osc x stopped operating stopped stopped stopped f : f : : : : cpu clk per osc x stopped operating stopped f stopped sub f : f : : : : cpu clk per osc x stopped operating stopped f stopped sub standby mode stop mode (tma3 = 0) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) (tma3 = 0) sby (standby) interrupt timers a, b, c serial, int , int 0 1 sby (standby) interrupt stop stop int , timer a 0 1 int , timer a 0 1 stop stop/sby (lson = 1) 4 2 3 1. time-base interrupt 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. dton is not affected f : f : f : f : : : : lson: dton: cyc sub osc x main oscillation frequency suboscillation frequency for time-base f /4 f /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag osc x cpu clk per active mode timers a, b, c serial, int , int 0 1 notes: * * * * * figure 9 mcu status transitions active mode: the mcu operates according to the clock generated by the system oscillators osc 1 and osc 2 . standby mode: the mcu enters standby mode when the sby instruction is executed from active mode. in this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all instruction execution-related clocks stop. the stopping of these clocks stops the cpu, retaining all ram and register contents and maintaining the current i/o pin status. standby mode is terminated by a reset input oran interrupt request. if it is terminated by a reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and resumes, executing
hd404818 series 29 the next instruction after the sby instruction. if the interrupt enable flag is 1, that interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 10. standby oscillator: active peripheral clocks: active all other clocks: stop reset = 1 ? no yes if0 = 1 ? no yes im0 = 0 ? if1 = 1 ? no yes im1 = 0 ? ifta = 1 ? no yes imta = 0 ? iftb = 1 ? no yes imtb = 0 ? iftc = 1 ? no yes imtc = 0 ? ifs = 1 ? no yes ims = 0 ? no yes no yes no yes no yes no yes no yes (sby only) (sby only) (sby only) watch oscillator: stop suboscillator: active peripheral clocks: stop all other clocks: stop restart processor clocks reset mcu execute next instruction accept interrupt execute next instruction (active mode) restart processor clocks no yes if = 1, im = 0, and ie = 1? (sby only) figure 10 mcu operating flowchart of watch and standby modes
hd404818 series 30 stop mode: the mcu enters stop mode if the stop instruction is executed in active mode when tma3 = 0. in this mode, the system oscillator stops, which stops all mcu functions as well. stop mode is terminated by a reset input as shown in figure 11. reset must be high for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed.
stop mode oscillator internal clock reset stop instruction execution t t (stabilization time) rc t res res 3 figure 11 timing of stop mode cancellation watch mode: the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details on reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson is 0, or subactive mode if lson is 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc t x 2t + t rc ) for an int 0 interrupt, as shown in figure 12. operation during mode transition is the same as that at standby mode cancellation (figure 10).
hd404818 series 31 active mode watch mode active mode oscillation stabilization period interrupt strobe int 0 interrupt request generation (during the transition from watch mode to active mode only) t t t rc t x t: t rc : interrupt frame length oscillation stabilization period figure 12 interrupt frame subactive mode: the cpu operates with a clock generated by the x1 and x2 oscillation circuits. functions that can operate in subactive mode are listed in table 16. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of lson and dton. the dton flag can only be set in subactive mode; it is automatically reset after a transition to active mode. subactive mode is an optional function that the user must specify on the function option list. interrupt frame: in watch and subactive modes, clk is supplied for timer a and the i nt 0 circuit. prescaler w and timer a operate as time bases to generate interrupt frame timing. three interrupt frame cycles (t) can be selected by the settings of the miscellaneous register, as shown in figure 13. in watch and subactive modes, timer a and int 0 interrupts are generated in synchronism with the interrupt frame. an interrupt request is generated at an interrupt strobe, except when the mcu enters active mode from watch mode. the int 0 falling edge is acknowledged regardless of the interrupt frame, but an interrupt is executed simultaneously with the second interrupt strobe. timer a generates an overflow and interrupt request at an interrupt strobe.
hd404818 series 32 mis2 mis1 mis0 t rc selection refer to table 20 mis: $00c mis 1 bit 0 bit 00 01 10 11 t 0.24414 ms 15.625 ms 62.5 ms not used 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms oscillation circuit condition external clock input ceramic or crystal oscillator notes: rc 1 2 t rc 1 1. the value of t applies only when using a 32.768-khz oscillator. 2. only direct transfer. * * * figure 13 miscellaneous register direct transfer: by controlling the dton, the mcu can be placed directly from subactive to active mode. the detailed procedure is as follows: set the dton flag in subactive mode while lson = 0. execute the stop or sby instruction. after the oscillation stabilization time (a fixed value), the mcu will move automatically from subactive to active mode. note that dton ($020, bit 3) is valid only in subactive mode. when the mcu is in active mode, this flag is always at reset. the transition time (t d ) from subactive to active mode is t rc < t d < t + t rc . subactive mode interrupt strobe direct transfer timing internal execution time (< t) oscillation stabilization time active mode t t rc t: t : rc stop/sby execution (lson = 0, dton = 1) interrupt frame period oscillation stabilization period figure 14 direct transfer timing mcu operating sequence: the mcu operates in the sequence shown in figures 15 to 17. it is reset by an asynchronous reset input, regardless of its state.
hd404818 series 33 the low-power mode operation sequence is shown in figure 17. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 1 ? reset mcu mcu operation cycle no yes figure 15 mcu operating sequence (power on)
hd404818 series 34 mcu operation cycle if = 1 ? instruction execution sby/stop instruction ? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1 ? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 16 mcu operating sequence (mcu operation cycle)
hd404818 series 35 low-power mode operation cycle if = 1 and im = 0 ? hardware nop execution ? pc next iocation mcu operation cycle standby/watch mode if = 1 and im = 0 ? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes for specific if and im, see figure 10, mcu operating flowchart figure 17 mcu operating sequence (low-power mode operation) notes on use: in subactive mode, a timer a interrupt request or an external interrupt request ( int 0 ) occurs in synchronism with an interrupt strobe. if the stop or sby instruction is executed at the same time with an interrupt strobe, these interrupt requests will be cancelled and the corresponding interrupt request flags (ifta, if0) will not be set. in subactive mode, do not use the stop or sby instruction at the time of an interrupt strobe.
hd404818 series 36 when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of int 0 is shorter than the interrupt frame, int 0 is not be detected. also, if the low level period after the falling edge of int 0 is shorter than the interrupt frame, int 0 is not be detected. edge detection is shown in figure 18. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes to low from high, a falling edge is detected. in figure 19, the level of the int 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge is not detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge is not detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than the interrupt frame. high low int sampling 0 low figure 18 edge detection a: low b: low int interrupt frame 0 a: high b: high int interrupt frame 0 (a) high level period (b) low level period figure 19 sampling example
hd404818 series 37 internal oscillator circuit figure 20 shows the block diagram of the internal oscillator circuit. a ceramic oscillator can be connected to osc 1 and osc 2 . a 32.768-khz crystal oscillator can be connected to x1 and x2. external clock operation is available for the system oscillator. f osc x2 x1 subsystem oscillator 1/4 divider circuit 1/8 divider circuit mode control circuit timing generator circuit osc f x cyc f sub f timing generator circuit system clock ( cpu ) system clock ( per ) timer-base clock ( clk ) osc system oscillator 1 2 figure 20 internal oscillator circuit $ % & ' , - ! "# $ ' ( )* + . / 0 d 0 reset osc 2 osc 1 v cc numg comp 1 /d 13 test x1 x2 gnd sck /r0 0 gnd figure 21 layout of crystal and ceramic oscillators
hd404818 series 38 table 18 examples of oscillator circuits circuit configuration circuit constants external clock operation oscillator osc open 1 osc 2 ceramic oscillator osc 2 c 1 2 c osc 1 r f ceramic gnd hd404812, hd404814, hd404816, hd404818, hd4074818 ceramic oscillator: csa4.00mg (murata) r f = 1m w 20% c 1 = c 2 = 30 pf 20% hd40l4812, hd40l4814, hd40l4816, hd40l4818, hd407l4818 ceramic oscillator: csb400p (murata) csb400p22 (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% csb800j (murata) csb800j122 (murata) r f = m w 20% c 1 = c 2 = 220 pf 5% crystal oscillator osc c 1 2 c osc crystal gnd l s c r s c 0 1 2 r f hd404812, hd404814, hd404816, hd404818, hd4074818 c 1 : 10 to 22 pf 20% c 2 : 10 to 22 pf 20% r f = 1 m w 20% crystal: equivalent to circut shown at bottom left. c 0 : 7 pf max. r s : 100 w max
hd404818 series 39 table 18 examples of oscillator circuits (cont) circuit configuration circuit constants crystal oscillator x1 c 1 2 c x2 crystal gnd l s c r s c 0 crystal: 32.768 khz: mx38t (nippon denpa kogyo) c 1 : = 20 pf 20% c 2 : = 20 pf 20% r s : = 14 k w c 0 : = 1.5 pf notes: 1. the circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. the circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. when using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. writing among osc 1 and osc 2 or x1 and x2, and other elements should be as short as possible, and should not cross other wires. refer to figure 21. 3. when the 32.768-khz crystal oscillator is not used, pin x1 must be fixed to v cc and pin x2 must be left open.
hd404818 series 40 input/output the mcu provides 26 i/o pins and 4 input-only pins including 10 high-current pins (15 ma max.). twenty-six i/o pins contain programmable pull-up mos. when each i/o pin is used as an input, the data control register (dcr) controls the output buffer. table 19 shows the i/o pin circuit types. the configuration of the i/o buffers is shown in table 19.
hd404818 series 41 table 19 i/o pin circuit types i/o pins circuit pin name i/o common pins (wint pull-up mos) v cc v cc input control signal input data output data pdr dcr pull-up control signal d 0 -d 9 r0 0 -r0 3 r1 0 -r1 3 r2 0 -r2 3 r3 0 -r3 3 v cc v cc sck output data sck (internal) dcr pull-up control signal sck output pins (with pull-up mos) v cc v cc output data so or timo dcr pull-up control signal so timo input pins v cc pdr pull-up control signal int 0 int 1 si input control signal input data d 10 d 11 /vc ref vc ref analog input input control input data mode select signal + d 12 /comp 0 d 13 /comp 1 (multiplexed with analog inputs) note: for ro 2 /so, refer to table 20, note 3.
hd404818 series 42 d port: consists of ten 1-bit i/o ports and four input ports. pins d 0 to d 9 are high-current i/o pins (15 ma max.). the sum of the current for all d-port pins is up to 100 ma. d port can be set/reset by the sed/red and sedd/redd instructions, and can be tested by the td/tdd instruction. output data is stored in the port data register. the output buffer for port d can be turned on/off by the d-port data control registers (dcrb, dcrc, dcrd). the dcr is located in the memory address area. pins d 10 to d 13 are input-only pins. two operation modes are available for pins d 12 and d 13 : digital input mode and analog input mode. the operation modes can be selected by port mode register b (pmrb; bits 1, 0). in the digital input mode, these pins can be used as input with the same characteristics as other i/o pins. in the analog input mode, users can read the result of the comparison between the reference voltage as input data. the reference voltage is input through d 11 /vc ref . r port: consists of four 4-bit i/o ports and can receive/transmit data by the lar/lra and lbr/lrb instructions. output data is stored in the port data register (pdr) of each pin. the output buffers of the r ports can be turned on/off by the r-port data control registers (dcr0?cr3). the dcr is located in the memory address area. pins r0 0 , r0 1 , and r0 2 are multiplexed with sck , si, and so, respectively. pins r3 1 , r3 2 , and r3 3 are multiplexed with timo, int 0 , and int 1 , respectively. refer to figure 23. pull-up mos transfer control: all i/o ports, except for pins d 10 ? 13 , contain programmable pull-up mos. bit 3 of port mode register b (pmrb3) controls the activation of all pull-up mos simultaneously. pull-up mos is controlled by the port data register (pdr) of each pin. therefore, each bit of pull-up mos can be individually turned on or off. refer to table 20. the on/off status of each transistor and the peripheral function mode of each pin can be set independently. unused i/o pins: if unused pins are left floating, the lsi may malfunction because of noise. the i/o pins should be fixed as follows to prevent this: pull-up to v cc through internal pull-up mos, or pull-up to v cc through a resistor of approximately 100 k w .
hd404818 series 43 mpx pin comparator + vc ref mode register internal bus figure 22 configuration of d12 and d13
hd404818 series 44 pmra (port mode register a) adr: $004 321 0 r0 /so pin mode selection 2 r0 /si pin mode selection 1 r3 / int pin mode selection 2 r3 / int pin mode selection 3 0 1 port select bit 3 0 1 r3 int 3 pmra 1 bit 2 pmra 0 1 r3 int 2 0 port select bit 1 pmra 0 1 r0 si 1 port select bit 0 pmra 0 1 r0 so 2 port select pull-up mos on/off bit 3 0 1 off on pmrb bit 2 pmrb 0 1 r3 timo 1 port select bit 1 pmrb 0 1 d comp 1 13 port select bit 0 pmrb 0 1 d comp 0 12 port select d /comp 0 pin mode selection 12 13 1 0 321 pmrb (port mode register b) adr: $012 d /comp 1 pin mode selection r3 /timo pin mode selection pull-up mos on/off selection port select bit 3 0 1 r0 sck 0 smr smr (serial mode register) adr: $005 r0 / sck pin mode selection 0 321 0 figure 23 i/o select mode registers
hd404818 series 45 table 20 input/output by program control pmrb bit 3 0 1 dcr0101 pdr 01 010 10 1 pmos (a) o n on nmos (b) on o n pull-up mos on o n notes: ?indicates off status. 1. combine the values of the above mode registers (pmrb3, dcr, and pdr) to select the input/output for pmos (a), nmos (b), and the pull-up mos, individually. the dcr and pdr control each pin. also, pmrb3 controls the on/off of all pull-up moss. 2. the second bit of the miscellaneous register (mis2) controls r0 2 /so. when mis2 is 1, pmos (a) is off. mis2 r0 2 /so pmos (a) 0on 1 off 3. each bit of dcr corresponds to each port as follows: dcr bit 3 bit 2 bit 1 bit 0 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 2 dcr3 r3 3 r3 2 r3 1 r3 0 dcrb d 3 d 2 d 1 d 0 dcrc d 7 d 6 d 5 d 4 dcrd d 9 d 8
hd404818 series 46 pmrb3 input control signal v cc pull-up mos dcr pdr input data nmos (b) pmos (a) v cc figure 24 configuration of the input/output buffer
hd404818 series 47 timers the mcu provides prescalers s and w (each with a different input clock source), and three timer/ counters (timers a, b, and c). figures 25, 26 and 27 show their diagrams. prescaler s: the input to prescaler s is the system clock signal. the prescaler is initialized to $000 by mcu reset, and starts to count up with the system clock signal as soon as the reset input goes low. the prescaler keeps counting up except at mcu reset and in the stop and watch modes. the prescaler provides input clock signals to timers a to c and the transmit clock of the serial interface. they can be selected by timer mode registers a (tma), b (tmb), c (tmc), and the serial mode register (smr), respectively. prescaler w: the input to prescaler w is a clock which divides the x1 input clock by 8. the output of prescaler w is available as an input clock for timer a by controlling timer mode register a (tma). timer a operation: after timer a is initialized to $00 by mcu reset, it counts up at every clock input signal. when the next clock signal is applied after timer a has counted up to $ff, timer a is set to $00 again, and an overflow output is generated. this sets the timer a interrupt request flag (ifta: $001, bit 2) to 1. therefore, timer a can function as an interval timer periodically generating overflow output at every 256th clock signal input (figure 25). to use timer a as a watch time base, set tma3 to 1. timer counter a receives prescaler w output, and timer a generates interrupts with accurate timing (reference clock = 32-khz crystal oscil lator). when using timer a as a watch time base, prescaler w and the timer counter can be initialized to $0 by setting timer mode register a. the clock input signals to timer a are selected by timer mode register a (tma: $008).
hd404818 series 48 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f sub 1/2 t subcyc (t subcyc ) f sub per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? figure 25 timer a block diagram
hd404818 series 49 timer b operation: timer mode register b (tmb: $009) selects the auto-reload function, input clock source, and prescaler divide ratio for timer b. when an external event input is used as an input clock signal to timer b, select r3 3 / int 1 as int 1 by port mode register a (pmra: $004) to prevent an external interrupt request from occurring (figure 26) timer b is initialized according to the data written into timer load register b by software. timer b counts up at every clock input signal. when the next clock signal is applied to timer b after it is set to $ff, it will generate an overflow output. in this case, if the auto-reload function is selected, timer b is initialized according to the value of timer load register b. if it is not selected, timer b goes to $00. the timer b interrupt request flag (iftb: $002, bit 0) will be set as this overflow is output. system clock int 1 selector prescaler s (pss) clock timer latch register bl (tlbl) timer counter b (tcb) timer load register bu (tlru) timer load register bl (tlrl) timer mode register b (tmb) timer b interrupt request flag (iftb) 3 internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? free-running control overflow f cyc /f sub (t cyc /t subcyc ) timer latch register bu (tlbu) figure 26 timer b block diagram timer c operation: timer mode register c (tmc: $00d) selects the auto-reload function and the prescaler divide ratio for timer c. timer c is initialized according to the data written into timer load register c by software. timer c counts up at every clock input signal. when the next clock signal is applied to timer c after it is set to $ff, it will generate an overflow output. in this case, if the auto-reload function is selected, timer c is initialized
hd404818 series 50 according to the value of timer load register c. if it is not selected, timer c goes to $00. the timer c interrupt request flag (iftc: $002, bit 2) will be set as this overflow is output. timer c is also available as a watchdog timer for detecting runaway programs. mcu reset occurs when the watchdog on flag (wdon) is 1 and the counter overflow output is generated by a runaway program. if timer c stops, the watchdog timer function also stops. in the standby mode, this function is enabled. timer c provides a variable duty-cycle pulse output function (pwm). the output waveform differs depending on the contents of the timer mode register and timer load register c (figure 28). when selecting the pulse output function, set r3 1 /timo to timo by controlling port mode register b. when timer c stops, this functions also stops. watchdog on flag (wdon) system reset signal timer c interrupt request flag (iftc) timer output control logic timer latch register cu (tlcu) timer latch register cl (tlcl) clock timer counter c (tcc) selector system clock prescaler s (pss) overflow internal data bus timer load register cu (tcru) timer load register cl (tcrl) timer mode register c (tmc) free-running/ reload control watchdog timer control logic timo 2 4 8 32 128 512 1024 2048 3 f cyc /f sub (t cyc /t subcyc ) figure 27 timer c block diagram
hd404818 series 51 t (tcr + 1) t 256 t t (256 ?tcr) tmc3 = 0 t: tcr: note: when tcr = $ff, this waveform is always fixed low. tmc3 = 1 input clock period to counter (see table 23) the value of the timer load register figure 28 variable duty-cycle pulse output waveform
hd404818 series 52 registers for timers timer mode register a (tma: $008): timer mode register a is a 4-bit write-only register which controls the timer a operation as table 21 shows. timer mode register a is initialized to $0 at mcu reset. timer mode register b (tmb: $009): timer mode register b (tmb) is a 4-bit write-only register which selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as shown in table 22. timer mode register b is initialized to $0 by mcu reset. the data of timer b changes at the second instruction cycle of a write instruction. initialization of timer b by writing data into timer load register b should be performed after the contents of tmb are changed. table 21 timer mode register a tma bit 3 bit 2 bit 1 bit 0 source prescaler, input clock period, operating mode 0 0 0 0 pss, 2048 t cyc timer a mode 1 pss, 1024 t cyc 1 0 pss, 512 t cyc 1 pss, 128 t cyc 1 0 0 pss, 32 t cyc 1 pss, 8 t cyc 1 0 pss, 4 t cyc 1 pss, 2 t cyc 1 0 0 0 psw, 32 t subcyc time-base mode 1 psw, 16 t subcyc 1 0 psw, 8 t subcyc 1 psw, 2 t subcyc 1 0 0 psw, 1/2 t subcyc 1 do not use 1 0 psw, tca reset 1 notes: 1. t subcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) 2. timer counter overflow output period (s) = input clock period (s) 256 3. if psw or tca reset is selected while the lcd is operating, lcd operation halts (power switch goes off). when the lcd is connected for display, the psw and tca reset periods must be set in the program to the minimum. 4. in time base mode, the timer counter overflow output cycle must be greater than half of the interrupt frame period (t/2 = t rc ). if 1/2 t subcyc is selected, t rc must be 7.8125 ms ((mis1, mis0) = (0, 1), see figure 13).
hd404818 series 53 5. the division ratio must not be modified during time base mode operation, otherwise an overflow cycle error will occur. timer mode register c (tmc: $00d): timer mode register c is a 4-bit write-only register which selects the auto-reload function, input clock source, and prescaler divide ratio, as table 23 shows. timer mode register c is initialized to $0 at mcu reset. the contents of timer mode register c will change in the second instruction cycle after a write instruction to tmc. therefore, it is required to initialize timer c after the contents of timer mode register c have been changed completely. timer b (tcbl: $00a, tcbu: $00b, tlrl: $00a, tlru: $00b): timer b consists of an 8-bit write- only timer load register, and an 8-bit read-only timer counter. each of them has low-order digits (tcbl: $00a, tlrl: $00a) and high-order digits (tcbu: $00b, tlru: $00b). (refer to figure 26.) timer counter b can be initialized by writing data into timer load register b. in this case, write the low- order digits first, and then the high-order digits. the timer counter is initialized when the high-order digit is written. the timer load register is initialized to $00 by mcu reset. the counter value of timer b can be obtained by reading timer counter b. in this case, read the high-order digits first, and then the low-order digits. the count value of the low-order digit is obtained when the high- order digit is read. timer c (tccl: $00e, tccu: $00f, tcrl: $00e, tcru: $00f): timer c consists of the 8-bit write- only timer load register and the 8-bit read-only timer counter. these individually consist of low-order digits (tccl: $00e, tcrl: $00e) and high-order digits (tccu: $00f, tcru: $00f). the operation mode of timer c is the same as that of timer b. table 22 timer mode register b tmb3 auto-reload function 0no 1 yes tmb2 tmb1 tmb0 prescaler divide ratio, clock input source 00 0 ? 2048 00 1 ? 512 01 0 ? 128 01 1 ? 32 10 0 ? 8 10 1 ? 4 11 0 ? 2 11 1 int 1 (external event input)
hd404818 series 54 table 23 timer mode register c tmc3 auto-reload function 0no 1 yes tmc2 tmc1 tmc0 prescaler divide ratio, clock input source 00 0 ? 2048 00 1 ? 1024 01 0 ? 512 01 1 ? 128 10 0 ? 32 10 1 ? 8 11 0 ? 4 11 1 ? 2 notes on use when using the timer output as variable duty-cycle pulse (pwm) output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 24. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle.
hd404818 series 55 table 24 pwm output following update of timer load register pwm output mode timer load register is updated during high pwm output timer load register is updated during low pwm output free running timer load register updated to value n interrupt request timer load register updated to value n interrupt request t (255 ?n) t (n + 1) t (n' + 1) t (255 ?n) t (n + 1) reload timer load register updated to value n interrupt request timer load register updated to value n interrupt request tt (255 ?n) t t t (255 ?n)t
hd404818 series 56 serial interface the serial interface transmits/receives 8-bit data serially. it consists of the serial data register, the serial mode register, port mode register a, the octal counter, and the selector (figure 29). pin r0 0 / sck and the transmit clock signal are controlled by the serial mode register. the data of the serial data register can be written and read by software. the data in the serial data register can be shifted synchronously with the transmit clock signal. the sts instruction starts serial interface operations and resets the octal counter to $0. the octal counter starts to count at the falling edge of the transmit clock signal ( sck ) and increments by one at the rising edge of the s c k . when the octal counter is reset to $0 after eight transmit clock signals, or when a transmit/receive operation is discontinued by resetting the octal counter, the serial interrupt request flag will be set. internal data bus ? 2 ? 8 ? 32 ? 128 ? 512 ? 2048 port mode register (pmra) sck selector system clock prescaler s (pss) i/o control logic 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 si so octal counter (oc) i/o control logic transfer control signal f cyc /f sub (t cyc /t subcyc ) figure 29 serial interface block diagram
hd404818 series 57 selection and change of the operation mode: table 25 shows the serial interface operation modes which are determined by a combination of the value in the port mode register and in the serial mode register. initialize the serial interface by writing to the serial mode register to change the operation mode of the serial interface. table 25 serial interface operation mode smr3 pmra1 pmra0 serial interface operating mode 1 0 0 clock continuous output mode 1 0 1 transmit mode 1 1 0 receive mode 1 1 1 transmit/receive mode operating state of serial interface: the serial interface has three operating states: the sts waiting state, transmit clock wait state, and transfer state (figure 30). the sts waiting state is the initialization state of the serial interface internal state. the serial interface enters this state in one of two ways: either by changing the operation mode through a change in the data in the port mode register, or by writing data into the serial mode register. in this state, the serial interface does not operate even if the transmit clock is applied. if the sts instruction is executed then, the serial interface shifts to the transmit clock wait state. in the transmit clock wait state, the falling edge of the first transmit clock causes the serial interface to shift to the transfer state, while the octal counter counts up and the serial data register shifts simultaneously. as an exception, if the clock continuous output mode is selected, the serial interface stays in transmit clock wait state while the transmit clock outputs continuously. the octal counter becomes 000 again after 8 external transmit clocks or by the execution of the sts instruction, the serial interface then returns to the transmit clock wait state, and the serial interrupt request flag is set simultaneously. in the transfer state the octal counter becomes 000 after 8 internal transmit clocks, the serial interface then enters the sts instruction waiting state, and the serial interrupt request flag is set simultaneously. when the internal transmit clock is selected, the transmit clock output is triggered by the execution of the sts instruction, and stops after 8 clocks. program the smr again to initialize the internal state of the serial interface when the pmra is programmed in the transfer state or in the transmit clock wait state. then the serial interface goes into the sts waiting state.
hd404818 series 58 (ifs ? 1) octal counter = 000 transmit clock disable sts waiting state transmit clock 8 external transmit clocks sts instruction transmit clock wait state (octal counter = 000) transfer state (octal counter 1 000) write to smr sts instruction smr write 8 internal transmit clocks (ifs ? 1) (ifs ? 1) figure 30 serial interface operation states example of transmit clock error detection: the serial interface malfunctions when the transmit clock is disturbed by external noise. in this case, transmit clock errors can be detected by the procedure shown in figure 31. if more than 8 transmit clocks are applied in the transmit clock wait state, the state of the serial interface shifts in the following sequence: transfer state, transmit clock wait state, and transfer state again. the serial interrupt request flag should be reset before entering into the sts waiting state by writing data to smr. this procedure causes the serial interface request flag to be set again.
hd404818 series 59 transmission finished (ifs ? 1) disable interrupt ifs ? 0 write to smr ifs = 1 ? normal end transmit clock error processing no yes figure 31 transmit clock error detection
hd404818 series 60 registers for serial interface serial mode register (smr: $005): the 4-bit write-only serial mode register controls the r0 0 / sck , prescaler divide ratio, and transmit clock source (table 26, figure 32). a write signal to the serial mode register controls the internal state of the serial interface. a write signal to the serial mode register stops the serial data register and octal counter from applying the transmit clock, and it also resets the octal counter to $0 simultaneously. therefore, when the serial interface is in the transfer state, a write signal causes the serial mode register to cease the data transfer and to set the serial interrupt request flag. data in the serial mode register will change in the second instruction cycle after a write instruction to the serial mode register. therefore, it is required to execute the sts instruction after the data in the serial mode register has been changed completely. the serial mode register will be reset to $0 by mcu reset. serial data register (srl: $006, sru: $007): the 8-bit read/write serial data register consists of low- order digits (srl: $006) and high-order digits (sru: $007). the data in the serial data register will be output from the so pin lsb first synchronously with the falling edge of the transmit clock signal. at the same time, external data will be input from the si pin to the serial data register synchronously with the rising edge of the transmit clock. figure 33 shows the i/o timing chart for the transmit clock signal and the data. the read/write operation of the serial data register should be performed after the completion of data transmit/receive. otherwise, data accuracy cannot be guaranteed. table 26 serial mode register smr3 r0 0 / sck 0 used as r0 0 port input/output pin 1 used as sck input/output pin transmit clock smr2 smr1 smr0 r0 0 / sck port clock source prescaler divide ratio system clock divide ratio 000 sck /output prescaler ? 2048 ? 4096 001 sck /output prescaler ? 512 ? 1024 010 sck /output prescaler ? 128 ? 256 011 sck /output prescaler ? 32 ? 64 100 sck /output prescaler ? 8 ? 16 101 sck /output prescaler ? 2 ? 4 110 sck /output system clock ? 1 111 sck /input external clock
hd404818 series 61 pmra3 pmra2 pmra1 pmra: $004 smr3 smr2 smr1 smr0 smr: $005 r0 2 /so pin mode selection transmit clock selection r0 0 / sck pin mode selection r0 1 /si pin mode selection pmra0 figure 32 configurations and functions of the mode registers lsb msb 12 345 6 78 transmit clock serial output data serial input data latch timing figure 33 serial interface i/o timing
hd404818 series 62 lcd controller/driver the mcu contains four common signal pins, the controller, and the driver. the controller and the driver drive 32 segment signal pins. the controller consists of display data ram, the lcd control register (lcr), and the lcd duty-cycle/clock control register (lmr) (figure 34). four programmable duty cycles and lcd clocks are available. since the mcu contains a dual port ram, display data can be transferred to segment signal pins automatically without program control. when selecting the 32-khz oscillation clock as the lcd clock source, the system allows the lcd to display even in watch mode, in which the system clock halts. v cc power switch v 1 v 2 v 3 gnd lcd common driver display on/off lcd duty- cycle/clock control register display control register lcd segment driver lcd clock $050 $06f ram area duty selection clock selection 22 3 lcd clock seg32 seg2 seg1 com4 com3 com2 com1 system clock dividing output (cl1?l3) 32-khz clock dividing output (cl0) 2 display area (dual port ram) lmr: $014 lcr: $013 1 lcd power supply control circuit figure 34 lcd controller/driver configuration lcd data area and segment data ($050 to $06f): figure 35 shows the configuration of the lcd ram area. each bit of this area, corresponding to four types of duty cycles, can be transmitted to the segment driver as display data by programming the area corresponding to the duty cycle.
hd404818 series 63 bit 3 bit 2 bit 1 bit 0 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05a $05b $05c $05d $05e $05f com4 com3 com2 com1 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 bit 3 bit 2 bit 1 bit 0 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 $06a $06b $06c $06d $06e $06f com4 com3 com2 com1 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 figure 35 configuration of lcd ram area (dual port ram) lcd control register (lcr: $013): the lcd control register is a 3-bit write-only register which controls the blanking of the lcd, activation of the power switch, and display in watch mode/subactive mode (table 27, figure 36). blank/display blank: segment signal is faded regardless of the lcd ram data. display: lcd ram data is transmitted as a segment signal. power switch on/off off: power switch is off. on: power switch is on and v 1 is v cc . watch mode/subactive mode display off: in the watch mode/subactive mode, all common/segment pins are fixed to gnd, and the power switch is off. on: in the watch mode/subactive mode, lcd ram data is transmitted as a segment signal. lcd duty-cycle/clock control register (lmr: $014): the lcd duty-cycle/clock control register is a write-only register which specifies four display duty cycles and the reference clock for the lcd (table 28, figure 36).
hd404818 series 64 table 27 lcd control register lcr bit 2 watch mode/ subactive mode display lcr bit 1 power switch on/off lcr bit 0 blank/ display 0 off 0 off 0 blank 1 o n 1 on 1 display note: with the lcd in watch mode, use the divider output of the 32-khz oscillator as an lcd clock and set lcr bit 2 to 1. when the system oscillator divider output is used as an lcd clock, set lcr bit 2 to 0. table 28 lcd duty-cycle/clock control register lmr bit 3 bit 2 bit 1 bit 0 duty cycle select/input clock select 0 0 1/4 duty cycle 0 1 1/3 duty cycle 1 0 1/2 duty cycle 1 1 static 0 0 cl0 (32.768 khz/64; when 32.768-khz oscillator is used) 0 1 cl1 (f cyc /256) 1 0 cl2 (f cyc /2048) 1 1 cl3 (refer to table 29) note: f cyc is the system oscillator divider output. 210 lcr (lcd control register) adr = $013 blank/display power switch on/off (not used) display on/off in watch mode duty cycle selection input clock selection 3210 lmr (lcd mode register) adr = $014 figure 36 lcd control register
hd404818 series 65 table 29 lcd frame frequency lmr static bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 instruction cycle time 00 011 01 1 cl0 cl1 cl2 cl3 * 10 m s 512 hz 390.6 hz 48.8 hz 24.4 hz/64 hz 1 m s 512 hz 3906 hz 488hz 244 hz/64 hz lmr 1/2 duty cycle bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 instruction cycle time 00 011 01 1 cl0 cl1 cl2 cl3 * 10 m s 256 hz 195.3 hz 24.4 hz 12.2 hz/32 hz 1 m s 256 hz 1953 hz 244 hz 122 hz/32 hz lmr 1/3 duty cycle bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 instruction cycle time 00 011 01 1 cl0 cl1 cl2 cl3 * 10 m s 170.6 hz 130.2 hz 16.3 hz 8.1 hz/21.3 hz 1 m s 170.6 hz 1302 hz 162.6 hz 81.3 hz/21.3 hz lmr 1/4 duty cycle bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 instruction cycle time 00 011 01 1 cl0 cl1 cl2 cl3 * 10 m s 128 hz 97.7 hz 12.2 hz 6.1 hz/16 hz 1 m s 128 hz 977 hz 122 hz 61 hz/16 hz note: * division ratio differs depending on the value of bit 3 of timer mode register a (tma3 = 0/tma3 = 1). if tma3 = 0, cl3 = fcyc x duty cycle/4096; if tma3 = 1, cl3 = 32.768 khz x duty cycle/512.
hd404818 series 66 large lcd panel driving and driving voltage (v lcd ): when using a large lcd panel, lower the dividing resistance by attaching external resistors in parallel with the internal dividing resistors (figure 37). since the liquid crystal display board is of a matrix configuration, the path of the charge/discharge current through the load capacitors is very complicated. moreover, since it varies depending on display conditions, the value of resistance cannot be determined by simply referring to the load capacitance of the liquid crystal display. the value of resistance must be experimentally determined according to the demand for power consumption of the equipment in which the liquid crystal display is implemented. capacitor c (0.1 to 0.3 m f) is recommended to be attached. in general, r is 1 k w to 10 k w . figure 37 shows a connection when changing the liquid crystal driving voltage (v lcd ). in this case, the power supply switch for the dividing resistors (power switch) must be turned off. (bit 1 of the lcr register is 0.)
hd404818 series 67 32 2 3 4 32 32 32 v cc v 2 v 3 gnd v 1 com1 seg1 to seg32 v cc v 2 v 3 gnd v 1 com1 com2 seg1 to seg32 v cc v 2 v 3 gnd v 1 com1 to com3 seg1 to seg32 v cc v 2 v 3 gnd v 1 com1 to com4 seg1 to seg32 v cc v lcd v cc v lcd v cc v lcd v cc v lcd r r r v (v ) cc 1 v 2 v 3 gnd r r r v (v ) cc 1 v 2 v 3 gnd c c c c = 0.1 to 0.3 f 4-digit lcd with signal . 8-digit lcd 10-digit lcd with signal 16-digit lcd . . . static drive 1/2 duty, 1/2 bias drive 1/3 duty, 1/3 bias drive 1/4 duty, 1/3 bias drive v v gnd cc lcd 3 3 figure 37 examples of lcd connections
hd404818 series 68 pin description in prom mode the hd4074818 and hd407l4818 are ztat ? microcomputers incorporating a prom. in the prom mode, the mcu does not operate and the hd4074818 and hd407l4818 can program the on-chip prom. pin number mcu mode prom mode pin number mcu mode prom mode fp- 80b fp-80a tfp-80 pin name i/o pin name i/o fp-80b fp-80a tfp-80 pin name i/o pin name i/o 179 d 2 i/o o 2 i/o 28 26 r2 3 i/o a 12 i 280 d 3 i/o o 3 i/o 29 27 r3 0 i/o a 13 i 31 d 4 i/o o 4 i/o 30 28 r3 1 /timo i/o a 14 i 42 d 5 i/o o 5 i/o 31 29 r3 2 / int 0 i/o ce i 53 d 6 i/o o 6 i/o 32 30 r3 3 / int 1 i/o oe i 64 d 7 i/o o 7 i/o 33 31 seg1 o 75 d 8 i/o 34 32 seg2 o 86 d 9 i/o 35 33 seg3 o 97 d 10 iv pp 36 34 seg4 o 10 8 d 11 /vc ref ia 9 i 3 7 3 5 seg5 o 11 9 d 12 /comp 0 i m 0 i 3 8 3 6 seg6 o 12 10 d 13 /comp 1 i m 1 i 3 9 3 7 seg7 o 13 11 test i test i 4 0 3 8 seg8 o 14 12 x1 i gnd 41 39 seg9 o 15 13 x2 o 4 2 4 0 seg10 o 16 14 gnd gnd 43 41 seg11 o 17 15 r0 0 / sck i/o a 1 i 4 4 4 2 seg12 o 18 16 r0 1 /si i/o a 2 i 4 5 4 3 seg13 o 19 17 r0 2 /so i/o a 3 i 4 6 4 4 seg14 o 20 18 r0 3 i/o a 4 i 4 7 4 5 seg15 o 21 19 r1 0 i/o a 5 i 4 8 4 6 seg16 o 22 20 r1 1 i/o a 6 i 4 9 4 7 seg17 o 23 21 r1 2 i/o a 7 i 5 0 4 8 seg18 o 24 22 r1 3 i/o a 8 i 5 1 4 9 seg19 o 25 23 r2 0 i/o a 0 i 5 2 5 0 seg20 o 26 24 r2 1 i/o a 10 i 5 3 5 1 seg21 o 27 25 r2 2 i/o a 11 i 5 4 5 2 seg22 o
hd404818 series 69 pin number mcu mode prom mode pin number mcu mode prom mode fp- 80b fp-80a tfp-80 pin name i/o pin name i/o fp-80b fp-80a tfp-80 pin name i/o pin name i/o 55 53 seg23 o 6 8 6 6 com4 o 56 54 seg24 o 6 9 6 7 v 1 57 55 seg25 o 7 0 6 8 v 2 58 56 seg26 o 7 1 6 9 v 3 v cc 59 57 seg27 o 7 2 7 0 numo 60 58 seg28 o 7 3 7 1 numo 61 59 seg29 o 7 4 7 2 numg v cc 62 60 seg30 o 7 5 7 3 v cc v cc 63 61 seg31 o 7 6 7 4 osc 1 iv cc 64 62 seg32 o 7 7 7 5 osc 2 o 65 63 com1 o 7 8 7 6 reset i reset i 66 64 com2 o 7 9 7 7 d 0 i/o o 0 i/o 67 65 com3 o 8 0 7 8 d 1 i/o o 1 i/o note: i/o: input/output pin, i: input pin, o: output pin
hd404818 series 70 programmable rom operation the mcu on-chip prom is programmed in prom mode. prom mode is set by pulling test , m 0 , and m 1 low, and reset high, as shown in figure 38. in prom mode, the mcu does not operate. it can be programmed like a standard 27256 eprom using a standard prom programmer and an 80-to-28-pin socket adapter. table 31 lists the recommended prom programmers and socket adapters. since an instruction of the hmcs400 series consists of 10 bits, the hmcs400 series microcomputer incorporates a conversion circuit to enable the use of a general-purpose prom programmer. by this circuit, an instruction is read or programmed using two addresses, a lower 5 bits and upper 5 bits. for example, if 8 kwords of on-chip prom are programmed by a general-purpose prom pro-grammer, 16 kbytes of addresses ($0000?3fff) should be specified. programming and verification the mcu can be programmed at high speed without causing voltage stress or affecting data reliability. table 30 shows how programming and verification modes are selected. precautions 1. addresses $0000 to $3fff must be specified if the prom is programmed by a prom programmer. if addresses of $4000 or higher are accessed, the prom may not be programmed or verified. note that plastic package types cannot be erased and reprogrammed. data in unused addresses must be set to $ff. 2. ensure that the prom programmer, socket adapter, and lsi match. using the wrong programmer for the socket adapter may cause an overvoltage and damage the lsi. make sure that the lsi is firmly fixed in the socket adapter, and that the socket adapter is firmly fixed onto the programmer. 3. the prom should be programmed with v pp = 12.5 v. other proms use 21 v. if 21 v is applied to the mcu, the lsi may be permanently damaged. 12.5 v is the intel 27256 setting. table 30 prom mode selection pin mode ce oe v pp o 0 ? 7 programming low high v pp data input verify high low v pp data output programming inhibited high high v pp high impedance
hd404818 series 71 table 31 prom programmers and socket adapters prom programmer socket adapter manufacturer type name manufacturer type name package type data i/o 121b 29b hitachi hs460esf01h fp-80b hs460esh01h fp-80a hs461est01h tfp-80 aval corp. pkw-1000 hitachi hs460esf01h fp-80b hs460esh01h fp-80a hs461est01h tfp-80 o to o 07 a to a 014 address a to a 014 data o to o 07 oe ce oe ce gnd v pp v cc v cc v pp reset test m m 0 1 v cc figure 38 prom mode dunction diagram
hd404818 series 72 addressing modes ram addressing modes as shown in figure 39, the mcu has three ram addressing modes: register indirect addressing, direct addressing, and memory register addressing. register indirect addressing mode: the w register, x register, and y register contents (10 bits total) are used as the ram address. direct addressing mode: a direct addressing instruction consists of two words, with the word (10 bits) following the opcode used as the ram address. memory register addressing mode: the memory registers (16 digits from $040 to $04f) are accessed by executing the lamr and xmra instructions. rom addressing modes and the p instruction the mcu has four kinds of rom addressing modes as shown in figure 40. direct addressing mode: the program can branch to any address in rom memory space by executing the jmpl, brl, or call instruction. these instructions replace the 14 program counter bits (pc 13 to pc 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 32 pages of rom with 256 words per page. by executing the br instruction, the program can branch to an address in the current page. this instruction replaces the lower eight bits of the program counter (pc 7 to pc 0 ) with 8-bit immediate data. when the br instruction is on a page boundary (256n + 255) (figure 41), executing it transfers the pc contents to the next page according to the hardware architecture. consequently, the program branches to the next page when the br instruction is used on a page boundary. the hmcs400 series cross macroassembler has an automatic paging facility for rom pages. zero-page addressing mode: by executing the cal instruction, the program can branch to the zero-page subroutine area, which is located at $0000?003f. when the cal instruction is executed, 6-bit immediate data is placed in the lower six bits of the program counter (pc 5 to pc 0 ) and 0s are placed in the higher eight bits (pc 13 to pc 6 ). table data addressing mode: by executing the tbr instruction, the program can branch to the address determined by the contents of the 4-bit immediate data, accumulator, and b register. p instruction: rom data addressed by table data addressing can be referenced by the p instruction (figure 42). when bit 8 in the referred rom data is 1, eight bits of rom data are written into the accumulator and b register. when bit 9 is 1, eight bits of rom data is written into the r1 and r2 port output registers. when both bits 8 and 9 are 1, rom data is written into the accumulator and b register, and also to the r1 and r2 port output registers at the same time.
hd404818 series 73 the p instruction has no effect on the program counter. ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 w 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 ram address direct addressing d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 instruction 2nd word opcode instruction 1st word ap 9 ap 8 ap 7 ap ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 ram address memory register addressing m 3 m 2 m 1 m 0 opcode instruction 000100 6 figure 39 ram addressing modes
hd404818 series 74 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 instruction 2nd word opcode instruction 1st word [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pcpcpcpc 10111213 program counter direct addressing zero page addressing a 5 a 4 a 3 a 2 a 1 a 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pcpc 10111213 program counter 00 000000 pcpc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pcpcpc 10111213 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 00 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pcpcpc 111213 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pcpc 8 pc p 0 p 1 p 2 p 3 figure 40 rom addressing modes
hd404818 series 75 br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 41 page boundary between br instruction and branch destination
hd404818 series 76 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referred rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 rarara 101112 13 b 2 b 3 b register 00 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern ro 9 rom data r2 32103 210 if ro = 1 9 output registers r1, r2 r2 r2 r2 r1 r1 r1 r1 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 42 p instruction
hd404818 series 77 absolute maximum ratings hd404812, hd404814, hd404816, hd404818, and hd4074818 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc +0.3 v total permissible input current ? i o 100 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 m a 4, 5 30 ma 4, 6 maximum output current ? o 4 m a 7, 8 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation should be under the conditions of the electrical characteristics. if these conditions are exceeded, it may cause a malfunction or affect the reliability of the lsi. 1. d 10 (v pp ) of the hd4074818. 2. total permissible input current is the sum of the input currents which flow in from all i/o pins to gnd simultaneously. 3. total permissible output current is the sum of the output currents which flow out from v cc to all i/o pins simultaneously. 4. maximum input current is the maximum amount of input current from each i/o pin to gnd. 5. r0?3. 6. d 0 ? 9 . 7. maximum output current is the maximum amount of output current from v cc to each i/o pin. 8. d 0 ? 9 and r0?3.
hd404818 series 78 hd40l4812, hd40l4814, hd40l4816, hd40l4818, and hd407l4818 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v total permissible input current ? i o 100 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 m a 4, 5 30 ma 4, 6 maximum output current ? o 4 m a 7, 8 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation should be under the conditions of the electrical characteristics. if these conditions are exceeded, it may cause a malfunction or affect the reliability of the lsi. 1. d 10 (v pp ) of the hd407l4818. 2. total permissible input current is the sum of the input currents which flow in from all i/o pins to gnd simultaneously. 3. total permissible output current is the sum of the output currents which flow out from v cc to all i/o pins simultaneously. 4. maximum input current is the maximum amount of input current from each i/o pin to gnd. 5. r0?3. 6. d 0 ? 9 . 7. maximum output current is the maximum amount of output current from v cc to each i/o pin. 8. d 0 ? 9 and r0?3.
hd404818 series 79 electrical characteristics for standard-voltage hd404812, hd404814, hd404816, hd404818, and hd4074818 electrical characteristics dc characteristics (hd404812, hd404814, hd404816, hd404818: v cc = 4 to 6 v; hd4074818: v cc = 4 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes input high voltage v ih reset, sck , int 0 , si, int 1 0.8v cc v cc + 0.3 v osc 1 v cc ?0.5 v cc + 0.3 v input low voltage v il reset, sck , int 0 , si, int 1 ?.3 0.2v cc v osc 1 ?.3 0.5 v output high voltage v oh sck , timo,so v cc ?1.0 v i oh = 1.0 ma output low voltage v ol sck , timo,so 0.4 v i ol = 1.6 ma input/output leakage current |i il | reset, sck , int 0 , int 1 , si, so, timo, osc 1 1 m av in = 0 v to v cc 1 stop mode retaining voltage v stop v cc 2 v without 32-khz oscillator 4 current dissipation in active mode i cc1 v cc 3.5 7 m a v cc = 5 v, f osc = 4 mhz 2 i cc2 v cc 612 mav cc = 5 v, f osc = 4 mhz 5 current dissipation in standby mode i sby v cc 1 2 ma v cc = 5 v, f osc = 4 mhz 3 current dissipation in subactive mode i sub v cc 150 300 m av cc = 5 v, lcd: on 75 150 m a6
hd404818 series 80 item symbol pin min typ max unit test condition notes current dissipation in watch mode (1) i wtc1 v cc 10 20 m av cc = 5 v, lcd: off current dissipation in watch mode (2) i wtc2 v cc 25 50 m av cc = 5 v, lcd: on current dissipation in stop mode i stop v cc 110 m av cc = 5 v, without 32-khz oscillator notes: 1. excluding output buffer current. 2. the mcu is in the reset state. input/output current does not flow. mcu in reset state reset, test : v cc 3. the timer operates and input/output current does not flow. mcu in standby mode input/output in reset state serial interface: stop reset: gnd test : v cc d 12 , d 13 : digital input mode 4. ram data retention. 5. d 12 /d 13 is in the analog input mode. input/output current does not flow. vc ref , d 12 , d 13 : gnd 6. applies to the hd404812, hd404814, hd404816, and hd404818.
hd404818 series 81 input/output characteristics for standard pins (hd404812, hd404814, hd404816, hd404818: v cc = 4 to 6 v; hd4074818: v cc = 4 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes input high voltage v ih d 10 ? 13 , r0?r3 0.7v cc v cc + 0.3 v input low voltage v il d 10 ? 13 , r0?3 ?.3 0.3v cc v output high voltage v oh r0?3 v cc ?1.0 v i oh = 1.0 ma pull-up mos current ? pu r0?3 30 100 180 m av cc = 5 v, v in = 0 v output low voltage v ol r0?3 0.4 v i ol = 1.6 ma input/output leakage current |i il |d 11 ? 13 , r0?r3 1 m av in = 0 v to v cc 1 d 10 1 m av in = 0 v to v cc 2 20 m av in = 0 v to v cc 3 input high voltage v iha d 12 , d 13 (analog compare mode) vc ref + 0.1 v input low voltage v ila d 12 , d 13 (analog compare mode) vc ref 0.1 v analog input voltage v cref 0v cc 1.2 v notes: 1. output buffer current is excluded. 2. applies to hd404812, hd404814, hd404816, and hd404818. 3. applies to hd4074818.
hd404818 series 82 input/output characteristics for high-current pins (hd404812, hd404814, hd404816, hd404818: v cc = 4 to 6 v; hd4074818: v cc = 4 to 5.5 v; gnd = 0v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition input high voltage v ih d 0 ? 9 0.7v cc v cc + 0.3 v input low voltage v il d 0 ? 9 ?.3 0.3v cc v output high voltage v oh d 0 ? 9 v cc ?1.0 v i oh = 1.0 ma pull-up mos current ? pu d 0 ? 9 30 100 180 m av cc = 5 v, v in = 0 v output low voltage v ol d 0 ? 9 2.0 v i ol = 15 ma, v cc = 4.5 to 6 v 0.4 v i ol = 1.6 ma input/output leakage current * |i il |d 0 ? 9 1 m av in = 0 v to v cc note: * output buffer current is excluded. liquid crystal circuit characteristics (hd404812, hd404814, hd404816, hd404818: v cc = 4 to 6 v; hd4074818: v cc = 4 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition note segment driver voltage drop v ds seg1 to seg32 0.6 v i d = 3 m a1 common driver voltage drop v dc com1 to com4 0.3 v i d = 3 m a1 lcd power supply dividing resistance r w 100 300 900 k w lcd voltage v lcd v 1 4v cc v2 notes: 1. voltage drops from pins v 1 , v 2 , v 3 , and gnd to each segment and common pin. 2. keep the relationship v cc 3 v 1 3 v 2 3 v 3 3 gnd when v lcd is supplied by an external power supply.
hd404818 series 83 ac characteristics (hd404812, hd404814, hd404816, hd404818: v cc = 4 to 6 v; hd4074818: v cc = 4 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes oscillation frequency f osc osc 1 , osc 2 1.6 4.0 4.2 mhz x1, x2 32.768 khz oscillation frequency f osc osc 1 , osc 2 (without 32 khz) 0.25 4.0 4.2 mhz instruction cycle time t cyc 0.95 1 2.5 m s 0.95 1 1 6 without 32 khz oscillator stabilization time t rc osc 1 , osc 2 30 ms crystal 1 7.5 ms ceramic f osc = 4 mhz 1 x1, x2 3 s t a = ?0 to 60 c2 external clock frequency f cp osc 1 1.6 4.2 mhz 3 0.25 4.2 mhz without 32 khz 3 external clock high width t cph osc 1 110 ns 3 external clock low width t cpl osc 1 110 ns 3 external clock rise time t cpr osc 1 20 ns 3 external clock fall time t cpf osc 1 20 ns 3 int 0 high width t ih int 0 2t cyc / t subcyc 4, 6 int 0 low width t il int 0 2t cyc / t subcyc 4, 6 int 1 high width t ih int 1 2t cyc 4 int 1 low width t il int 1 2t cyc 4
hd404818 series 84 item symbol pin min typ max unit test condition notes reset high width t rsth reset 2 t cyc 5 input capacitance c in d 10 15 pf f = 1 mhz, v in = 0 v 8 90 pf f = 1 mhz, v in = 0 v 9 all pins except d 10 15 pf f = 1 mhz, v in = 0 v reset fall time t rstf 20 ms 5 analog comparator stabilization time t cstb d 12 , d 13 2t cyc 7 notes: 1. the oscillator stabilization time is the period up until the time the oscillator stabilizes after v cc reaches 4.0 v at power-on, or after reset goes high. at power-on or stop mode release, reset must be kept high for at least t rc . since t rc depends on the ceramic oscillator? circuit constant and stray capacitance, consult with the manufacturer when designing the reset circuit. 2. the oscillator stabilization time is the period up until the time the oscillator stabilizes after v cc reaches 4.0 v at power-on. the time required to stabilize the oscillator (t rc ) must be obtained. since t rc depends on the crystal circuit constant and stray capacitance, consult with the manufacturer. 3. see figure 43. 4. see figure 44. the unit t cyc is applied when the mcu is in standby mode or active mode. 5. see figure 45. 6. see figure 44. the unit t subcyc is applied when the mcu is in watch mode or subactive mode. t subcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) 7. the analog comparator stabilization time is the period up until the analog comparator stabilizes and correct data can be read after placing d 12 /d 13 into analog input mode. 8. applies to hd404812, hd404814, hd404816, and hd404818. 9. applies to hd4074818.
hd404818 series 85 serial interface timing characteristics during transmit clock output (hd404812, hd404814, hd404816, hd404818: v cc = 4 to 6 v; hd4074818: v cc = 4 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes transmit clock cycle time t scyc sck 1 t cyc / t subcyc 1, 2, 4 transmit clock high and low widths t sckh, t sckl sck 0.5 t scyc 1, 2 transmit clock rise and fall times t sckr, t sckf sck 100 ns 1, 2 serial output data delay time t dso so 300 ns 1, 2 serial input data setup time t ssi si 200 ns 1 serial input data hold time t hsi si 150 ns 1 during transmit clock input item symbol pin min typ max unit test condition notes transmit clock cycle time t scyc sck 1 t cyc / t subcyc 1, 4 transmit clock high and low widths t sckh, t sckl sck 0.5 t scyc 1 transmit clock rise and fall times t sckr, t sckf sck 100 ns 1 serial output data delay time t dso so 300 ns 1, 2 serial input data setup time t ssi si 200 ns 1 serial input data hold time t hsi si 150 ns 1 transmit clock completion detect time t sckhd sck 1 t cyc / t subcyc 1,2, 3, 4 notes: 1. see figure 46. 2. see figure 47. 3. the transmit clock completion detect time is the high level period after 8 pulses of transmit clocks are input. the serial interrupt request flag is not set if the next transmit clock is input before the transmit clock completion detect time has passed. 4. the unit t subcyc is applied when the mcu is in subactive mode. t subcyc = 244.14 m s (for a 32.768- khz crystal oscillator).
hd404818 series 86 t cpr t cpf v cc ?0.5 v 0.5 v osc 1 t cph t cpl 1/f cp figure 43 oscillator timing 0.8v cc 0.2v cc int 0 , int 1 t ih t il figure 44 interrupt timing reset t rstf t rsth 0.8v cc 0.2v cc figure 45 reset timing 0.8v cc 0.2v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.8 v v ?2.0 v cc v ?2.0 v (0.8v ) cc 0.8 v (0.2v ) sck so si after 8 pulses are input v ?2.0 v and 0.8 v are the threshold voltages for transmit clock output. 0.8v and 0.2v are the threshold voltages for transmit clock input. cc cc cc cc cc t sckh t sckhd * * * note: figure 46 serial interface timing
hd404818 series 87 test point 30 pf c 12 k w r v cc r = 2.6 k l w 1s2074 h or equivalent figure 47 timing load circuit
hd404818 series 88 electrical characteristics for low-voltage versions hd40l4812, hd40l4814, hd40l4816, hd40l4818, and hd407l4818 electrical characteristics dc characteristics (hd40l4812, hd40l4814, hd40l4816, hd40l4818: v cc = 2.7 to 6 v; hd407l4818: v cc = 3 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes input high voltage v ih reset, sck , int 0 , si, int 1 0.9v cc v cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v input low voltage v il reset, sck , int 0 , si, int 1 ?.3 0.1v cc v osc 1 ?.3 0.3 v output high voltage v oh sck , timo, so v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck , timo, so 0.4 v i ol = 0.4 ma input/output leakage current |i il | reset, sck , int 0 , int 1 , si, so, timo, osc 1 1 m av in = 0 v to v cc 1 stop mode retaining voltage v stop v cc 2 v without 32-khz oscillator 4 current dissipation in active mode i cc1 v cc 400 1000 m av cc = 3v, f osc = 400 khz 2 i cc2 v cc 1 2 ma v cc = 3 v, f osc = 400 khz, analog input mode (d 12 /d 13 ) 5 current dissipation in standby mode i sby v cc 200 500 m av cc = 3 v f osc = 400 khz 3 current dissipation in subactive mode i sub v cc 50 100 m av cc = 3 v, lcd: on 35 70 m a6
hd404818 series 89 item symbol pin min typ max unit test condition notes current dissipation in watch mode (1) i wtc1 v cc 515 m av cc = 3 v, lcd: off current dissipation in watch mode (2) i wtc2 v cc 15 35 m av cc = 3 v, lcd: on current dissipation in stop mode i stop v cc 110 m av cc = 3 v, without 32-khz oscillator notes: 1. excluding output buffer current. 2. the mcu is in the reset state. input/output current does not flow. mcu in reset state reset, test : v cc 3. the timer operates and input/output current does not flow. mcu in standby mode input/output in reset state serial interface: stop reset: gnd test : v cc d 0 ? 13 , r0?3: v cc d 12 , d 13 : digital input mode 4. ram data retention. 5. d 12 /d 13 is in the analog input mode. input/output current does not flow. vc ref , d 12 , d 13 : gnd 6. applies to hd40l4812, hd40l4814, hd40l4816, and hd40l4818.
hd404818 series 90 input/output characteristics for standard pins (hd40l4812, hd40l4814, hd40l4816, hd40l4818: v cc = 2.7 to 6 v; hd407l4818: v cc = 3 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes input high voltage v ih d 10 ? 13 , r0?3 0.7v cc v cc + 0.3 v input low voltage v il d 10 ? 13 , r0?3 ?.3 0.3v cc v output high voltage v oh r0?3 v cc ?.0 v i oh = 0.5 ma pull-up mos current ? pu r0?3 5 4 0 9 0 m av cc = 3 v, v in = 0 v output low voltage v ol r0?3 0.4 v i ol = 0.4 ma input/output leakage current |i il |d 11 ? 13 , r0?3 1 m av in = 0 v to v cc 1 d 10 1 m av in = 0 v to v cc 2 20 m av in = 0 v to v cc 3 input high voltage v iha d 12 , d 13 (analog compare mode) vc ref + 0.1 v input low voltage v ila d 12 , d 13 (analog compare mode) vc ref 0.1 v analog input voltage v cref 0v cc 1.2 v notes: 1 output buffer current is excluded. 2. applies to hd40l4812, hd40l4814, hd40l4816, and hd40l4818. 3. applies to hd407l4818.
hd404818 series 91 input/output characteristics for high-current pins (hd40l4812, hd40l4814, hd40l4816, hd40l4818: v cc = 2.7 to 6 v; hd407l4818: v cc = 3 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition input high voltage v ih d 0 ? 9 0.7v cc v cc + 0.3 v input low voltage v il d 0 ? 9 ?.3 0.3v cc v output high voltage v oh d 0 ? 9 v cc ?.0 v i oh = 0.5 ma pull-up mos current ? pu d 0 ? 9 54090 m av cc = 3 v, v in = 0 v output low voltage v ol d 0 ? 9 2.0 v i ol = 15 ma, v cc = 4.5 to 6 v 0.4 v i ol = 0.4 ma input/output leakage current * |i il |d 0 ? 9 1 m av in = 0 v ?v cc note: * output buffer current is excluded. liquid crystal circuit characteristics (hd40l4812, hd40l4814, hd40l4816, hd40l4818: v cc = 2.7 to 6 v; hd407l4818: v cc = 3 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes segment driver voltage drop v ds seg1 to seg32 0.6 v i d = 3 m a1 common driver voltage drop v dc com1 to com4 0.3 v i d = 3 m a1 lcd power supply dividing resistance r w 100 300 900 k w lcd voltage v lcd v 1 2.7 v cc v 2, 3 notes: 1. voltage drops from pins v 1 , v 2 , v 3 , and gnd to each segment and common pin. 2. keep the relation v cc 3 v 1 3 v 2 3 v 3 3 gnd when v lcd is supplied by an external power supply. 3. v lcd min. = 2.7 v (hd40l4812, hd40l4814, hd40l4816, hd40l4818) v lcd min. = 3 v (hd407l4818)
hd404818 series 92 ac characteristics (hd40l4812, hd40l4814, hd40l4816, hd40l4818: v cc = 2.7 to 6 v; hd407l4818: v cc = 3 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes oscillation frequency f osc osc 1 , osc 2 250 800 900 khz x1, x2 32.768 khz instruction cycle time t cyc 4.45 5 1 6 m s oscillator stabilization time t rc osc 1 , osc 2 7.5 ms f osc = 400 khz 1 7.5 ms f osc = 800 khz 1 x1, x2 3 s t a = ?0 to 60 c2 external clock frequency f cp osc 1 250 900 khz 3 external clock high width t cph osc 1 525 ns 3 external clock low width t cpl osc 1 525 ns 3 external clock rise time t cpr osc 1 30 ns 3 external clock fall time t cpf osc 1 30 ns 3 int 0 high width t ih int 0 2t cyc/ t subcyc 4, 6 int 0 low width t il int 0 2t cyc/ t subcyc 4, 6 int 1 high width t ih int 1 2t cyc 4 int 1 low width t il int 1 2t cyc 4 reset high width t rsth reset 2 t cyc 5 input capacitance c in d 10 15 pf f = 1 mhz, v in = 0 v 8 90 pf f = 1 mhz, v in = 0 v 9 all pins except d 10 15 pf f = 1 mhz, v in = 0 v reset fall time t rstf 20 ms 5 analog comparator stabilization time t cstb d 12 , d 13 2t cyc 7 notes: 1. the oscillator stabilization time is the period from when v cc reaches 2.7 v (hd407l4818: v cc = 3.0 v) at power-on until the oscillator stabilizes, or after reset goes high. at power-on or when recovering from stop mode, reset must be kept high for more than t rc . since t rc depends on the ceramic oscillator? circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer when designing the reset circuit.
hd404818 series 93 2. the oscillator stabilization time is the period from when v cc reaches 2.7 v (hd407l4818: v cc = 3.0 v) at power-on until the oscillator stabilizes. the time required to stabilize the oscillator (t rc ) must be obtained. since t rc depends on the ceramic oscillator? circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer. 3. see figure 48. 4. see figure 49. the unit t cyc is applied when the mcu is in standby mode or active mode. 5. see figure 50. 6. see figure 49. the unit t subcyc is applied when the mcu is in watch mode or subactive mode. t subcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) 7. the analog comparator stabilization time is the period from when d 12 /d 13 is placed in analog input mode until the analog comparator stabilizes and correct data can be read. 8. applies to hd40l4812, hd40l4814, hd40l4816, and hd40l4818. 9. applies to hd407l4818. serial interface timing characteristics during transmit clock output (hd40l4812, hd40l4814, hd40l4816, hd40l4818: v cc = 2.7 to 6 v; hd407l4818: v cc = 3 to 5.5 v; gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes transmit clock cycle time t scyc sck 1 t cyc / t subcyc 1, 2, 4 transmit clock high and low widths t sckh , t sckl sck 0.5 t scyc 1, 2 transmit clock rise and fall times t sckr , t sckf sck 200 ns 1, 2 serial output data delay time t dso so 500 ns 1, 2 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1
hd404818 series 94 during transmit clock input item symbol pin(s) min typ max unit test condition notes transmit clock cycle time t scyc sck 1 t cyc / t subcyc 1, 4 transmit clock high and low widths t sckh , t sckl sck 0.5 t scyc 1 transmit clock rise and fall times t sckr , t sckf sck 200 ns 1 serial output data delay time t dso so 500 ns 1, 2 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1 transmit clock completion detect time t sckhd sck 1 t cyc / t subcyc 1, 2, 3, 4 notes: 1. see figure 51. 2 see figure 52. 3. the transmit clock completion detect time is the high level period after 8 pulses of transmit clocks are input. the serial interrupt request flag is not set if the next transmit clock is input before the transmit clock completion detect time has passed. 4. t subcyc is applied when the mcu is in subactive mode. t subcyc = 244.14 m s (for a 32.768-khz crystal oscillator). t cpr t cpf v cc ?0.3 v 0.3 v osc 1 t cph t cpl 1/f cp figure 48 oscillator timing 0.9v cc 0.1v cc int 0 , int 1 t ih t il figure 49 interrupt timing reset t rstf t rsth 0.9v cc 0.1v cc figure 50 reset timing
hd404818 series 95 0.9v cc 0.1v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?1.0 v cc v ?1.0 v (0.9v ) cc 0.4 v (0.1v ) sck so si after 8 pulses are input v ?1.0 v and 0.4 v are the threshold voltages for transmit clock output. 0.9v and 0.1v are the threshold voltages for transmit clock input. cc cc cc cc cc t sckh t sckhd * * * note: figure 51 timing of serial interface test point 30 pf c 12 k w r v cc r = 2.6 k l w 1s2074 h or equivalent figure 52 timing load circuit
hd404818 series 96 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as an 8-kword version (hd404818 and hd40l4818). an 8-kword data size is required to change rom data to mask manufacturing data since the program used is for an 8-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (2,048 words) not used vector address zero-page subroutine (64 words) pattern (4,096 words) not used rom 2-kword version: hd404812, hd40l4812 address $0800?1fff rom 6-kword version: hd404816, hd40l4816 address $1800?1fff $0000 $000f $0010 $003f $0040 $07ff $0800 $0000 $000f $0010 $003f $0040 $17ff $1800 $1fff fill this area with 1s vector address zero-page subroutine (64 words) pattern & program (4,096 words) not used rom 4-kword version: hd404814, hd40l4814 address $1000?1fff $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff program (6,144 words) $0fff $1000
hd404818 series 97 hd404812, hd404814, hd404816, hd404818, hd40l4812, hd40l4814, hd40l4816, hd40l4818 option list 5-v operation low-voltage operation 5-v operation low-voltage operation 5-v operation low-voltage operation 5-v operation low-voltage operation 1. rom size 3. rom code media eprom: the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. with 32-khz cpu operation and with watch time base without 32-khz cpu operation and with watch time base without 32-khz cpu operation and without watch time base 2. optional functions * * date of order customer department name rom code name lsi type number (hitachi? entry) / / 4. oscillator ceramic oscillator crystal oscillator external clock f = f = f = mhz mhz mhz fp-80a fp-80b tfp-80 6. package note: used not used 5. stop mode options marked with an asterisk require a subsystem crystal oscillator (x1, x2). please check off the appropriate applications and enter the necessary information. hd404812 hd40l4812 hd404814 hd40l4814 hd404816 hd40l4816 hd404818 hd40l4818 2-kword 4-kword 6-kword 8-kword * please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version).
hd404818 series 98 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan.

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